Adaptive Gate-Level Voltage Scaling Using Dual Voltage Domino Logic

Power consumption is a growing problem in modern digital design, and due to the quadratic relationship between power consumption and supply voltage, significant low-power research has focused on reducing the supply voltage. Adaptive gate-level voltage scaling (AGVS) is a novel design technique which dynamically adjusts the supply voltage at the gate-level to maximize energy efficiency. We propose dual voltage domino logic (DVDL) as a new logic style that is suitable for AGVS designs and use a 32-bit DVDL ripple carry adder to investigate the potential for AGVS. Several alternative control logic schemes are discussed including single-bit versus multi-bit carrychecks and sequential precharging versus concurrent precharging. Simulation results show a 13% savings in energy when using an AGVS adder in place of a standard domino logic adder in the ALU of a simple RISC processor.